An Integrated Design and CAD Approach for Efficient Power Delivery in Multicore Processors

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).

The objective of this research is to develop solutions that ensure reliable power delivery in high-performance multicore systems. Technology trends for multicore chips show increased on-chip noise sources, decreasing supply voltage levels, and reduced headroom for noise: together these make the problem of on-chip power supply noise, which can cause a circuit to be nonfunctional, acutely difficult. The approach is based on an integrated strategy that incorporates novel design techniques, bolstered by computer-aided design (CAD) strategies to build reliable on-chip power distribution systems.

The design thrust of the project will develop novel multicore-specific circuits, including switched decoupling capacitor (decap) circuits and active decaps, to actively cancel the supply noise in cores that suffer from large switching current. The modeling and CAD aspects will focus on analyzing multicore power grids containing a mix of these novel structures and traditional methods, and optimizing these grids using pre-silicon. Additionally, the PIs will develop CAD techniques to build adaptive structures into the circuit in the pre-silicon phase, in order to enable sensor-driven adaptive post-silicon power grid noise mitigation.

Solutions from this research will facilitate the design of next-generation high-performance, low-voltage systems for computing and communication applications, and will be demonstrated on prototype implementations. The PIs plan to transfer technology through direct industrial collaborations, particularly leveraging this project's connections with the Semiconductor Research Corporation. The PIs will proactively recruit and nurture students from under-represented groups and develop new course materials for the undergraduate and graduate curriculum in the areas of electronics, chip design, and CAD.