CAREER: Computer-Aided Design of Mixed ASIC / Reconfigurable Fabrics of the Nanometer Era

PROPOSAL NO: 0347891

INSTITUTION: U of Minnesota-Twin Cities

PRINCIPAL INVESTIGATOR: Bazargan, Kia

TITLE: Computer-Aided Design of Mixed ASIC / Reconfigurable Fabrics of the Nanometer Era

Abstract:

Improvements in the chip manufacturing technology have brought about astonishing growth of electronic systems, resulting in multi-gigahertz clock speeds and billion-gate chips. However, explosive complexities, rising manufacturing costs, shrinking time-to-market windows, and deep submicron effects are threatening the continuation of the growth in the electronics technology. New system complexities result in unreliability (even failure) and unpredictability of system behavior. Employing FPGA-like (Field Programmable Gate Array) reconfigurable blocks in SoC promotes flexibility and drives non-recurring engineering (NRE) costs down.

Embedded FPGA-like reconfigurable fabrics have emerged as part of todays SoC, and will inevitably be part of future designs because of the enormous advantages they provide. However, there are many challenging hurdles in way of employing reconfigurable fabrics within SoC. This proposal tackles a number of these challenges: 1) Statistical modeling and optimization at different levels of abstraction are proposed to take on the reliability and predictability concerns. 2) Architectural features for the reconfigurable fabrics are also investigated to reduce power and improve thermal conduction out of the fabric, while optimizing the flexibility, cost and performance. 3) CAD algorithms for mixed ASIC / reconfigurable fabric are proposed, and include hierarchical evaluation and estimation of uncertain designs, low power optimization and technology mapping.

The proposed algorithms and methodologies would consider flexibility, reliability and productivity as first-class citizens to be optimized along with other design quality metrics such as area, cost, and performance. We will incorporate some of the results of this research in the VLSI courses at the University of Minnesota, as well as an advanced course on reconfigurable computing. Furthermore, a web page will be developed that would host all course material, reconfigurable benchmarks and FPGA tools from our group and other researchers.