Collaborative Research: SHF: Medium: Automated energy-efficient sensor data winnowing using native analog processing

As computing becomes pervasive in all aspects of daily life, computing hardware must allow for increasing interaction with the physical world. This interaction takes the form of sensed signals that are analog in nature, e.g., a sensor may output a voltage that can take on a continuous range of values. Traditional mainstream computing digitizes this data, converting it to digital 0s and 1s for efficient analysis and processing. However, as the amount of sensed analog data is growing exponentially, digital processors will be faced with a data deluge from external sensors. For these vast volumes of data, even the cost of converting analog input data to digital signals, prior to any processing, can be prohibitively expensive. Native analog processing (NAP) negates the need for analog-to-digital conversion by working in the analog domain. NAP can be used to implement data processing functions inexpensively, but can achieve only limited accuracy; on the other hand, digital processing can achieve high accuracy, but requires the overhead of analog-to-digital conversion. This project presents a methodology for mixed-signal processing that hybridizes digital and analog subcircuit implementations to achieve the best of both worlds. The effort intends to actively engage with the semiconductor industry, and will train graduate and undergraduate students in the area of semiconductor design, thus alleviating the national skills shortage in this area.In the first step, computing tasks are automatically partitioned into hybrid analog/digital segments, with the goal of meeting system-level constraints on throughput, power, and noise/error. The computations associated with a task are abstractly represented by a dataflow graph (DFG). This representation is widely used to model a variety of tasks, including those commonly used in digital signal processing and machine learning. The nodes in the DFG are mapped to analog or digital implementations, using cost functions that represent the cost of implementation, as well as the cost of any required analog-to-digital or digital-to-analog conversion. Next, the analog and digital circuitry is optimized to build a silicon implementation at the layout level, based on cutting-edge transistor technologies, which involve restrictive design rules that impose limitations such as unidirectional routing and gridded layout. The optimizations are facilitated by novel techniques for back-end analysis, synthesis, and implementation developed in this project, including transistor and interconnect optimizations, placement and routing techniques that are specifically targeted to mixed-signal designs, and compact performance machine-learning-based model generation that efficiently predicts circuit performance. The project thus automatically translates the system-level DFG specification of a computing task to an optimized mixed-signal silicon implementation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.