CSR:Small: Efficient FTL Buffer Management for High-Performance Solid State Drives

In the past several decades, the access time of magnetic disks has improved about 8% per year while processor speeds have improved at an astounding 60% per year. The tremendous performance disparity between disks and processors means that many large-scale applications are limited by the performance of the underlying storage systems. Flash memory is an emerging storage technology that shows tremendous promise to compensate for the limitations of magnetic disk-based storage devices. A key advantage of flash-based storage is that its read-write performance is much better than disk. Flash memory-based storage like solid state drives provides fast random access to all areas of the device. On the other hand, writes to flash memory are much slower than reads. Furthermore, writes to flash must be preceded by an erase unless a clean block is used, and the number of erase cycles is limited. To overcome these drawbacks, a Flash Translation Layer (FTL) is designed to provide dynamic address mapping between logical addresses to physical addresses, wear-leveling, garbage collection, and buffer caching. A small memory buffer in FTL is used to perform these functions.

This project will focus on techniques to use the least amount of memory buffer to achieve high performance and low energy consumption. The research tasks include efficient heuristics for hot and cold data classification and how to reduce memory requirement for wear-leveling and garbage collection. This effort will improve the fundamental understanding of flash memory and will extend the capability of flash memory to support many critical applications.