NER: Characterizing and Modeling Magnetic Tunnel Junction Devices for a Spintronics-based Processor

The objective of this research is to demonstrate the feasibility of using spintronics-based magnetic tunnel junction devices to implement complex digital systems. The approach is to design and fabricate a single-bit full adder at the NSF-supported University of Minnesota Nanofabrication Center using the prototype magnetic tunnel junction devices previously demonstrated by the investigators. Concurrently with this fabrication process, a multi-operation bit-serial function unit that will take advantage of the programmability of the magnetic gates will be designed and simulated. The ultimate goal beyond this initial feasibility study is to design a fully functional processor entirely from these novel non-charge-based spintronics devices.

The primary intellectual merit of this project is the development of new techniques and circuits that will lead to an understanding of how to construct complex computational elements from the magnetic tunnel junction gates. The innovative exploitation of this emerging technology will significantly expand the understanding of spintronics devices to eventually incorporate the potential advantages of this technology into future systems. Due to the highly exploratory nature of this work, it is unlikely that it would be pursued by industry. Yet it holds tremendous promise to help drive future computing trends, making it very appropriate for government support.

Broader impacts of this project include multidisciplinary training of a new generation of researchers that emphasizes both device fabrication and computing, and opportunities for underrepresented groups to participate in an exciting new research area. Existing collaborations will help to quickly transfer to industry the novel technology developed in this project.