Performance-Driven Layout

This research is on a unified way to consider both timing and geometric constraints during the placement process. The approach is to convert timing constraints to geometric shapes using 'defined windows'. A window represents a region in which all the modules along a given path can be placed without degrading the circuit performance. Then, based on the window information, a constructive placement process is used to select an unplaced module and to find an appropriate position for the module. Algorithms for the following issues are being studied: path elimination, window and region construction, module selection, module placement and path breaking, and slack distribution.