RIA: VLSI Architecture Designs for High-Speed Signal and Image Processing

This project develops algorithms and architectures for high-speed implementations of digital signal and image processing applications. Based on previous results on lookahead, decomposition, and incremental computation techniques for hardware-efficient implementation of high- speed linear recursive and adaptive digital filters, a method is developed to transform these algorithms into equivalent forms, which can operate at sample rates beyond the inherent limits in the original algorithms. Extensions are being carried out on these techniques to nonlinear recursions, such as dynamic programming, quantizer loops, adaptive differential pulse code modulation, and adaptive decision feedback equalization. Implementations for these algorithms in bit- serial, nibble-serial, and bit-parallel architectures are currently under study. The computational needs in many real-time signal and image processing algorithms can only be met by dedicated implementations. Success of dedicated designs require appropriate choice of algorithms architectures, and implementation methodologies. A complete examination of the algorithm and architecture approaches, as studied in this project, will provide the application-specific designer a wide design space, which can be exploited to obtain more efficient implementations. This research will impact future integrated design environments for VLSI implementations of dedicated signal and image processing applications.