SHF: Small: Enabling Resiliency in Nanometer-Scale CMOS Circuits

Modern integrated circuit design involves multibillion-transistor CMOS circuits, built using miniscule nanometer-scale transistors and wires. Such technologies are plagued by significant variations due to process uncertainties, supply voltage degradation, temperature changes, and aging phenomena, all of which are projected to grow more critical in the coming years. With variability steadily eating into design margins and yield, mainstream current-day methodologies will be unsustainable in the future and new approaches will be necessary. Such variations can be reduced by design optimization at the presilicon stage, before manufacturing, as well as at the postsilicon stage, after manufacturing. The focus of this work is to build design-for-adaptability techniques at the presilicon stage that enable postsilicon adjustments that allow circuits to recover from variational effects. The methods to be pursued will seek to inject formalism into the process of building a practical framework for designing resilient systems. A key ingredient is the development of new sensors and incorporates them into schemes that are capable of providing runtime adaptation, based on a sensing/mitigation strategy that forms a feedback loop, and ?cures? a ?sick? die.

Solutions from this research will facilitate the design of next-generation integrated systems for computing and communication applications, and has the potential to impact applications in the consumer, computing, and healthcare spaces. The technology developed in this project will be transferred to industry through research discussions as well as publications. The key accomplishments will be distributed through the PI?s research webpage. The project will actively recruit underrepresented minorities to the research project, and will contribute to education through the development of new course materials.