SHF: Small: Stress Management in Integrated Circuits

Speed and power are key attributes of a digital electronic integrated circuit that translate to system-level metrics such as response times and battery life in electronic systems. With progress in technology, these performance parameters are found to be increasingly dependent on thermal and mechanical stress in the system. This stress may be intentionally introduced (intrinsic stress) to enhance circuit performance, or may be unintentional (extrinsic stress) due to design factors or due to the environment faced by individual transistors in the circuit. The goal of this proposal is to enable a systematic and scientific approach to full-chip performance analysis and optimization in the presence of stress, through the development of (a) fast modeling approaches (b) optimization techniques that invoke the modeling solutions.

The current state of the art in stress modeling shows few to no significant approaches for full-chip analysis of stress effects, and stress optimization is rarely performed in a systematic way. This project will develop novel analytical and semi-analytical modeling techniques that are computationally efficient and scalable, permitting fast analysis of commonly encountered structures. The approach will draw upon a toolbox of stress analysis frameworks, tailoring them to on-chip environments and seeking new efficiencies. Full-chip analysis will be performed by invoking the modeling techniques on critical segments of the design to determine the drift in timing and power. The project will perform stress optimization at both the pre-silicon stage and the post-silicon stage. The research goals of the project will be supplemented by educational efforts as well as technology transfer efforts to industry.