Abstract
An ultra-fast frequency hopping spread spectrum transceiver front-end architecture is presented that provides 20dB of processing gain at RF for the first time. This enables the receiver front-end to supress any in-band interferes by 20dB before they arrive at the LNA. The circuit consists of passive mixers and agile digital oscillator/DAC engines that are capable of quickly moving in the frequency domain with very low power. A transient hop time of 1.5ns is achieved in this design. The front-end implemented in 65nm CMOS technology, occupies an active area of 3.lmm2, and consumes 24mW (=PTX=PRX) from a 1V power supply for a center frequency of 1GHz.
Original language | English (US) |
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Title of host publication | ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 246-249 |
Number of pages | 4 |
ISBN (Electronic) | 9781538654040 |
DOIs | |
State | Published - Oct 16 2018 |
Event | 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 - Dresden, Germany Duration: Sep 3 2018 → Sep 6 2018 |
Publication series
Name | ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference |
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Other
Other | 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 |
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Country/Territory | Germany |
City | Dresden |
Period | 9/3/18 → 9/6/18 |
Bibliographical note
Funding Information:ACKNOWLEDGMENT This research work was funded under the DARPA SPAR program (grant no. HR0011-17-2-0001).
Publisher Copyright:
© 2018 IEEE.