@inproceedings{e10aba6cea6b4cb89260fb449aad5121,
title = "A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer",
abstract = " An 8 Gb/s time-to-digital converter (TDC) based receiver with a time-based front-end in 65nm CMOS is specifically designed for in-package serial link applications. The proposed receiver converts the channel signal to a corresponding time delay which is amplified by a novel delay line based time amplifier. Next, a time-to-digital converter generates a 4-bit code which is used for digital equalization. The proposed design is digital intensive and hence highly resilient to voltage headroom and/or PVT issues. A bathtub curve and time domain eye-diagram were measured by an in-situ bit-error-rate (BER) monitor circuit. An energy-efficiency of 2.1 pJ/b was achieved at 8 Gb/s for a 7 mm link. The receiver area is 240×120μm 2 . ",
keywords = "Time-based, digital equalization, digital intensive, inverter-based, system-in-package (SiP), time-to-digital converter (TDC)",
author = "Chiu, {Po Wei} and Muqing Liu and Qianying Tang and Kim, {Chris H.}",
year = "2018",
month = dec,
day = "14",
doi = "10.1109/ASSCC.2018.8579267",
language = "English (US)",
series = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "187--190",
booktitle = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",
note = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 ; Conference date: 05-11-2018 Through 07-11-2018",
}