A fully integrated digital LDO with built-in adaptive sampling and active voltage positioning using a beat-frequency quantizer

Somnath Kundu; Muqing Liu; Shi Jie Wen; Richard Wong; Chris H. Kim

doi:10.1109/JSSC.2018.2870558

A fully integrated digital LDO with built-in adaptive sampling and active voltage positioning using a beat-frequency quantizer

Somnath Kundu, Muqing Liu, Shi Jie Wen, Richard Wong, Chris H. Kim

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

55 Scopus citations

Abstract

This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-frequency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology. A time-based approach, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer, makes the design highly digital. A D-flip-flop is utilized as a BF generator, which is used as the sampling clock for the DLDO. The variable sampling frequency in the BF DLDO can achieve fast response, LP consumption, and excellent stability at the same time. In addition to that, the DLDO has a built-in active voltage positioning (AVP) for lower peak-to-peak voltage deviation during load step. The load capacitor is only 40 pF, and the total core area of the DLDO is 0.0374 mm². A 50-mA step in load current produces a voltage droop of 108 mV, which is recovered in 1.24 μs. It can operate for a wide input voltage from 0.6 to 1.2 V while generating a 0.4-1.1-V output for a maximum load current of 100 mA. The peak current efficiency is 99.5% and the figure of merit (FOM) is 1.38 ps.

Original language	English (US)
Article number	8478195
Pages (from-to)	109-120
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	54
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2018.2870558
State	Published - Jan 2019

Bibliographical note

Funding Information:
Manuscript received April 23, 2018; revised July 3, 2018 and August 21, 2018; accepted September 3, 2018. Date of publication October 1, 2018; date of current version January 14, 2019. This work was supported in part by Cisco Systems and in part by the National Science Foundation under Grant CCF-1255937. This paper was approved by Guest Editor Wim Dehaene. (Corresponding author: Chris H. Kim.) S. Kundu was with the Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN 55455 USA. He is now with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: kundu006@umn.edu).

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

Active voltage positioning (AVP)
adaptive sampling
analog-to-digital converter (ADC)
low dropout (LDO) regulator
time quantizer
voltage regulator
voltage-controlled oscillator (VCO)
voltage-to-time converter

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title = "A fully integrated digital LDO with built-in adaptive sampling and active voltage positioning using a beat-frequency quantizer",

abstract = "This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-frequency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology. A time-based approach, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer, makes the design highly digital. A D-flip-flop is utilized as a BF generator, which is used as the sampling clock for the DLDO. The variable sampling frequency in the BF DLDO can achieve fast response, LP consumption, and excellent stability at the same time. In addition to that, the DLDO has a built-in active voltage positioning (AVP) for lower peak-to-peak voltage deviation during load step. The load capacitor is only 40 pF, and the total core area of the DLDO is 0.0374 mm2. A 50-mA step in load current produces a voltage droop of 108 mV, which is recovered in 1.24 μs. It can operate for a wide input voltage from 0.6 to 1.2 V while generating a 0.4-1.1-V output for a maximum load current of 100 mA. The peak current efficiency is 99.5% and the figure of merit (FOM) is 1.38 ps.",

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AB - This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-frequency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology. A time-based approach, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer, makes the design highly digital. A D-flip-flop is utilized as a BF generator, which is used as the sampling clock for the DLDO. The variable sampling frequency in the BF DLDO can achieve fast response, LP consumption, and excellent stability at the same time. In addition to that, the DLDO has a built-in active voltage positioning (AVP) for lower peak-to-peak voltage deviation during load step. The load capacitor is only 40 pF, and the total core area of the DLDO is 0.0374 mm2. A 50-mA step in load current produces a voltage droop of 108 mV, which is recovered in 1.24 μs. It can operate for a wide input voltage from 0.6 to 1.2 V while generating a 0.4-1.1-V output for a maximum load current of 100 mA. The peak current efficiency is 99.5% and the figure of merit (FOM) is 1.38 ps.

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A fully integrated digital LDO with built-in adaptive sampling and active voltage positioning using a beat-frequency quantizer

Abstract

Bibliographical note

Keywords

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