Abstract
The split-radix fast Fourier transform (SRFFT) is attractive for low-power FFT processors as it has the lowest numbers of multiplication operations among all FFT algorithms. FFT algorithms differ from one another by the location of the twiddle factor. The irregular locations of the twiddle factors in the SRFFT lead to complex address generators for the memory containing the twiddle factors. This paper proposes a novel twiddle factor addressing architecture for the split-radix FFT processor, which can effectively reduce its power consumption. This is then used to design a simple memory address generator and a low-power pipelined SRFFT. The proposed algorithm is used to implement a 1024-point pipelined circuit. Post-layout simulation shows that the proposed 1024-point design achieves over 24% and 14.7% lower power consumption for the multiplications and ROM, respectively, compared to a traditional radix-2 single delay feedback (SDF) FFT architecture.
| Original language | English (US) |
|---|---|
| Article number | 105276 |
| Journal | Microelectronics Journal |
| Volume | 117 |
| DOIs | |
| State | Published - Nov 2021 |
Bibliographical note
Funding Information:*This work was supported in part by the National Natural Science Foundation of China under Grant 61774049 , in part by the National Key R&D Program of China under No. 2018YFB2201000 and No. 2019YFE0120700 , and in part by the Shanghai Municipal Commission of Economy and Informatization under Grant PKX2020-D10 .
Publisher Copyright:
© 2021
Keywords
- Low-power
- Pipelining
- Single-delay feedback
- Split-radix fast fourier transform (SRFFT)
- Twiddle factor