A Reconfigurable 74-140 Mbps LDPC Decoding System for CCSDS Standard

Yun Chen; Jimin Wang; Shixian Li; Jinfou Xie; Qichen Zhang; Keshab K. Parhi; Xiaoyang Zeng

doi:10.1587/transfun.2020KEP0006

A Reconfigurable 74-140 Mbps LDPC Decoding System for CCSDS Standard

Yun Chen, Jimin Wang, Shixian Li, Jinfou Xie, Qichen Zhang, Keshab K. Parhi, Xiaoyang Zeng

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

AccumulateRepeat-4 Jagged-Accumulate (AR4JA) codes, which are channel codes designed for deep-space communications, are a series of QC-LDPC codes. Structures of these codes' generator matrix can be exploited to design reconfigurable encoders. To make the decoder reconfigurable and achieve shorter convergence time, turbo-like decoding message passing (TDMP) is chosen as the hardware decoder's decoding schedule and normalized min-sum algorithm (NMSA) is used as decoding algorithm to reduce hardware complexity. In this paper, we propose a reconfigurable decoder and present its FPGA implementation results. The decoder can achieve throughput greater than 74 Mbps.

Original language	English (US)
Pages (from-to)	1509-1515
Number of pages	7
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E104.A
Issue number	11
DOIs	https://doi.org/10.1587/transfun.2020KEP0006
State	Published - Nov 2021

Bibliographical note

Publisher Copyright:
© 2021 The Institute of Electronics, Information and Communication Engineers.

Keywords

QC-LDPC
decoder
encoder
reconfigurable architecture

Access

10.1587/transfun.2020KEP0006

OpenUrl availability

Full text

Cite this

@article{44aae754cb5e40a69b1e24f04348a7b0,

title = "A Reconfigurable 74-140 Mbps LDPC Decoding System for CCSDS Standard",

abstract = "AccumulateRepeat-4 Jagged-Accumulate (AR4JA) codes, which are channel codes designed for deep-space communications, are a series of QC-LDPC codes. Structures of these codes' generator matrix can be exploited to design reconfigurable encoders. To make the decoder reconfigurable and achieve shorter convergence time, turbo-like decoding message passing (TDMP) is chosen as the hardware decoder's decoding schedule and normalized min-sum algorithm (NMSA) is used as decoding algorithm to reduce hardware complexity. In this paper, we propose a reconfigurable decoder and present its FPGA implementation results. The decoder can achieve throughput greater than 74 Mbps.",

keywords = "QC-LDPC, decoder, encoder, reconfigurable architecture",

author = "Yun Chen and Jimin Wang and Shixian Li and Jinfou Xie and Qichen Zhang and Parhi, {Keshab K.} and Xiaoyang Zeng",

note = "Publisher Copyright: {\textcopyright} 2021 The Institute of Electronics, Information and Communication Engineers.",

year = "2021",

month = nov,

doi = "10.1587/transfun.2020KEP0006",

language = "English (US)",

volume = "E104.A",

pages = "1509--1515",

journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",

issn = "0916-8508",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "11",

}

TY - JOUR

T1 - A Reconfigurable 74-140 Mbps LDPC Decoding System for CCSDS Standard

AU - Chen, Yun

AU - Wang, Jimin

AU - Li, Shixian

AU - Xie, Jinfou

AU - Zhang, Qichen

AU - Parhi, Keshab K.

AU - Zeng, Xiaoyang

PY - 2021/11

Y1 - 2021/11

N2 - AccumulateRepeat-4 Jagged-Accumulate (AR4JA) codes, which are channel codes designed for deep-space communications, are a series of QC-LDPC codes. Structures of these codes' generator matrix can be exploited to design reconfigurable encoders. To make the decoder reconfigurable and achieve shorter convergence time, turbo-like decoding message passing (TDMP) is chosen as the hardware decoder's decoding schedule and normalized min-sum algorithm (NMSA) is used as decoding algorithm to reduce hardware complexity. In this paper, we propose a reconfigurable decoder and present its FPGA implementation results. The decoder can achieve throughput greater than 74 Mbps.

AB - AccumulateRepeat-4 Jagged-Accumulate (AR4JA) codes, which are channel codes designed for deep-space communications, are a series of QC-LDPC codes. Structures of these codes' generator matrix can be exploited to design reconfigurable encoders. To make the decoder reconfigurable and achieve shorter convergence time, turbo-like decoding message passing (TDMP) is chosen as the hardware decoder's decoding schedule and normalized min-sum algorithm (NMSA) is used as decoding algorithm to reduce hardware complexity. In this paper, we propose a reconfigurable decoder and present its FPGA implementation results. The decoder can achieve throughput greater than 74 Mbps.

KW - QC-LDPC

KW - decoder

KW - encoder

KW - reconfigurable architecture

UR - http://www.scopus.com/inward/record.url?scp=85159369580&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85159369580&partnerID=8YFLogxK

U2 - 10.1587/transfun.2020KEP0006

DO - 10.1587/transfun.2020KEP0006

M3 - Article

AN - SCOPUS:85159369580

SN - 0916-8508

VL - E104.A

SP - 1509

EP - 1515

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

IS - 11

ER -

A Reconfigurable 74-140 Mbps LDPC Decoding System for CCSDS Standard

Abstract

Bibliographical note

Keywords

Access

OpenUrl availability

Other files and links

Fingerprint

Cite this