TY - GEN
T1 - A simple technique to reduce clock jitter effects in continuous-time delta-sigma modulators
AU - Chang, Hairong
AU - Tang, Hua
PY - 2008
Y1 - 2008
N2 - Continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In this paper, we present a simple technique to reduce clock jitter effects. The technique employs two delayed elements to generate a feedback current waveform with a fixed-width return-to-zero time period, followed a fixed-width time period for active feedback, which is followed by another variable return-to-zero time period subject to clock jitter. It has been shown in the paper through behavioral simulation models that this technique is very effective to reduce independent clock jitter effects.
AB - Continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In this paper, we present a simple technique to reduce clock jitter effects. The technique employs two delayed elements to generate a feedback current waveform with a fixed-width return-to-zero time period, followed a fixed-width time period for active feedback, which is followed by another variable return-to-zero time period subject to clock jitter. It has been shown in the paper through behavioral simulation models that this technique is very effective to reduce independent clock jitter effects.
KW - Clock jitter effects
KW - Continuous-time
KW - Delta-sigma modulator
UR - http://www.scopus.com/inward/record.url?scp=51749114863&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51749114863&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2008.4541806
DO - 10.1109/ISCAS.2008.4541806
M3 - Conference contribution
AN - SCOPUS:51749114863
SN - 9781424416844
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1870
EP - 1873
BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Y2 - 18 May 2008 through 21 May 2008
ER -