All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits

Gyusung Park; Minsu Kim; Chris H. Kim; Bongjin Kim; Vijay Reddy

doi:10.1109/IRPS.2018.8353613

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits

Gyusung Park, Minsu Kim, Chris H. Kim, Bongjin Kim, Vijay Reddy

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Using simple on-chip monitoring circuits, we precisely characterized the impact of hot carrier injection and bias temperature instability on frequency and phase noise degradation of a 65nm all-digital PLL circuit. Experimental data shows that PLL phase noise degrades with aging even though the output frequency is maintained constant due to the PLL feedback operation. Results show that applying high temperature annealing can recover most of the phase noise degradation.

Original language	English (US)
Title of host publication	2018 IEEE International Reliability Physics Symposium, IRPS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	5C.21-5C.26
ISBN (Electronic)	9781538654798
DOIs	https://doi.org/10.1109/IRPS.2018.8353613
State	Published - May 25 2018
Event	2018 IEEE International Reliability Physics Symposium, IRPS 2018 - Burlingame, United States Duration: Mar 11 2018 → Mar 15 2018

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
Volume	2018-March
ISSN (Print)	1541-7026

Other

Other	2018 IEEE International Reliability Physics Symposium, IRPS 2018
Country/Territory	United States
City	Burlingame
Period	3/11/18 → 3/15/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

Bias temperature instability (BTI)
hot carrier injection (HCI)
phase noise
phase-locked loop (PLL)
thermal recovery

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10.1109/IRPS.2018.8353613

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Park, G., Kim, M., Kim, C. H., Kim, B., & Reddy, V. (2018). All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. In 2018 IEEE International Reliability Physics Symposium, IRPS 2018 (pp. 5C.21-5C.26). (IEEE International Reliability Physics Symposium Proceedings; Vol. 2018-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2018.8353613

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. / Park, Gyusung; Kim, Minsu; Kim, Chris H. et al.
2018 IEEE International Reliability Physics Symposium, IRPS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 5C.21-5C.26 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, G, Kim, M, Kim, CH, Kim, B & Reddy, V 2018, All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. in 2018 IEEE International Reliability Physics Symposium, IRPS 2018. IEEE International Reliability Physics Symposium Proceedings, vol. 2018-March, Institute of Electrical and Electronics Engineers Inc., pp. 5C.21-5C.26, 2018 IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, United States, 3/11/18. https://doi.org/10.1109/IRPS.2018.8353613

Park G, Kim M, Kim CH, Kim B, Reddy V. All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. In 2018 IEEE International Reliability Physics Symposium, IRPS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 5C.21-5C.26. (IEEE International Reliability Physics Symposium Proceedings). doi: 10.1109/IRPS.2018.8353613

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abstract = "Using simple on-chip monitoring circuits, we precisely characterized the impact of hot carrier injection and bias temperature instability on frequency and phase noise degradation of a 65nm all-digital PLL circuit. Experimental data shows that PLL phase noise degrades with aging even though the output frequency is maintained constant due to the PLL feedback operation. Results show that applying high temperature annealing can recover most of the phase noise degradation.",

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All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits

Abstract

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Keywords

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