An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer

Tonmoy Dhar; Jitesh Poojary; Ramesh Harjani; Sachin S. Sapatnekar

doi:10.1016/j.microrel.2023.114912

An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer

Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

Temporal degradation of transistors due to aging causes mismatch in the current mirror, a matching-critical building block of current digital to analog converters (IDACs). This mismatch induces non-linearity in IDAC behavior and can cause nonmonotonicity in the worst case. This paper performs an application-driven analysis of IDAC aging within a feed-forward equalizer (FFE) context. The work first models the effect of aging-induced mismatch over IDAC performance metrics and analyzes the performance shifts of IDACs over different topologies and input distributions. Next, the work illustrates how IDAC aging affects FFE behavior and presents novel schemes for FFE calibration to counter the impact of IDAC aging effectively.

Original language	English (US)
Article number	114912
Journal	Microelectronics Reliability
Volume	142
DOIs	https://doi.org/10.1016/j.microrel.2023.114912
State	Published - Mar 2023

Bibliographical note

Publisher Copyright:
© 2023 Elsevier Ltd

Keywords

Aging
Current mirror
Equalizer
IDAC
Mismatch

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abstract = "Temporal degradation of transistors due to aging causes mismatch in the current mirror, a matching-critical building block of current digital to analog converters (IDACs). This mismatch induces non-linearity in IDAC behavior and can cause nonmonotonicity in the worst case. This paper performs an application-driven analysis of IDAC aging within a feed-forward equalizer (FFE) context. The work first models the effect of aging-induced mismatch over IDAC performance metrics and analyzes the performance shifts of IDACs over different topologies and input distributions. Next, the work illustrates how IDAC aging affects FFE behavior and presents novel schemes for FFE calibration to counter the impact of IDAC aging effectively.",

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AU - Sapatnekar, Sachin S.

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AB - Temporal degradation of transistors due to aging causes mismatch in the current mirror, a matching-critical building block of current digital to analog converters (IDACs). This mismatch induces non-linearity in IDAC behavior and can cause nonmonotonicity in the worst case. This paper performs an application-driven analysis of IDAC aging within a feed-forward equalizer (FFE) context. The work first models the effect of aging-induced mismatch over IDAC performance metrics and analyzes the performance shifts of IDACs over different topologies and input distributions. Next, the work illustrates how IDAC aging affects FFE behavior and presents novel schemes for FFE calibration to counter the impact of IDAC aging effectively.

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KW - Equalizer

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An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer

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