An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

Bingzhe Li; M. Hassan Najafi; David J. Lilja

doi:10.1109/ASAP.2015.7245709

An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

Bingzhe Li, M. Hassan Najafi, David J. Lilja

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

26 Scopus citations

Abstract

Artificial neural networks (ANNs) usually require a very large number of computation nodes and can be implemented either in software or directly in hardware, such as FPGAs. Software-based approaches are offline and not suitable for real-time applications, but they support a large number of nodes. FPGA-based implementations, in contrast, can greatly speedup the computation time. However, resource limitations in an FPGA restrict the maximum number of computation nodes in hardware-based approaches. This work exploits stochastic bit streams to implement the Restricted Boltzmann Machine (RBM) handwritten digit recognition application completely on an FPGA. Exploiting this approach saves a large number of hardware resources making the FPGA-based implementation of large ANNs feasible.

Original language	English (US)
Title of host publication	Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	68-69
Number of pages	2
ISBN (Electronic)	9781479919246
DOIs	https://doi.org/10.1109/ASAP.2015.7245709
State	Published - Sep 8 2015
Event	26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 - Toronto, Canada Duration: Jul 27 2015 → Jul 29 2015

Publication series

Name	Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume	2015-September
ISSN (Print)	1063-6862

Other

Other	26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015
Country/Territory	Canada
City	Toronto
Period	7/27/15 → 7/29/15

Access

10.1109/ASAP.2015.7245709

OpenUrl availability

Full text

Cite this

Li, B., Najafi, M. H., & Lilja, D. J. (2015). An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams. In Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors (pp. 68-69). Article 7245709 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2015-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2015.7245709

An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams. / Li, Bingzhe; Najafi, M. Hassan; Lilja, David J.
Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors. Institute of Electrical and Electronics Engineers Inc., 2015. p. 68-69 7245709 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2015-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, B, Najafi, MH & Lilja, DJ 2015, An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams. in Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors., 7245709, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, vol. 2015-September, Institute of Electrical and Electronics Engineers Inc., pp. 68-69, 26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015, Toronto, Canada, 7/27/15. https://doi.org/10.1109/ASAP.2015.7245709

Li B, Najafi MH, Lilja DJ. An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams. In Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors. Institute of Electrical and Electronics Engineers Inc. 2015. p. 68-69. 7245709. (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors). doi: 10.1109/ASAP.2015.7245709

Li, Bingzhe ; Najafi, M. Hassan ; Lilja, David J. / An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams. Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 68-69 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).

@inproceedings{108ead0fa9d04ce7aaf1014be8cdfd34,

title = "An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams",

abstract = "Artificial neural networks (ANNs) usually require a very large number of computation nodes and can be implemented either in software or directly in hardware, such as FPGAs. Software-based approaches are offline and not suitable for real-time applications, but they support a large number of nodes. FPGA-based implementations, in contrast, can greatly speedup the computation time. However, resource limitations in an FPGA restrict the maximum number of computation nodes in hardware-based approaches. This work exploits stochastic bit streams to implement the Restricted Boltzmann Machine (RBM) handwritten digit recognition application completely on an FPGA. Exploiting this approach saves a large number of hardware resources making the FPGA-based implementation of large ANNs feasible.",

author = "Bingzhe Li and Najafi, {M. Hassan} and Lilja, {David J.}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE. Copyright: Copyright 2016 Elsevier B.V., All rights reserved.; 26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 ; Conference date: 27-07-2015 Through 29-07-2015",

year = "2015",

month = sep,

day = "8",

doi = "10.1109/ASAP.2015.7245709",

language = "English (US)",

series = "Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "68--69",

booktitle = "Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors",

}

TY - GEN

T1 - An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

AU - Li, Bingzhe

AU - Najafi, M. Hassan

AU - Lilja, David J.

PY - 2015/9/8

Y1 - 2015/9/8

N2 - Artificial neural networks (ANNs) usually require a very large number of computation nodes and can be implemented either in software or directly in hardware, such as FPGAs. Software-based approaches are offline and not suitable for real-time applications, but they support a large number of nodes. FPGA-based implementations, in contrast, can greatly speedup the computation time. However, resource limitations in an FPGA restrict the maximum number of computation nodes in hardware-based approaches. This work exploits stochastic bit streams to implement the Restricted Boltzmann Machine (RBM) handwritten digit recognition application completely on an FPGA. Exploiting this approach saves a large number of hardware resources making the FPGA-based implementation of large ANNs feasible.

AB - Artificial neural networks (ANNs) usually require a very large number of computation nodes and can be implemented either in software or directly in hardware, such as FPGAs. Software-based approaches are offline and not suitable for real-time applications, but they support a large number of nodes. FPGA-based implementations, in contrast, can greatly speedup the computation time. However, resource limitations in an FPGA restrict the maximum number of computation nodes in hardware-based approaches. This work exploits stochastic bit streams to implement the Restricted Boltzmann Machine (RBM) handwritten digit recognition application completely on an FPGA. Exploiting this approach saves a large number of hardware resources making the FPGA-based implementation of large ANNs feasible.

UR - http://www.scopus.com/inward/record.url?scp=84955591146&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84955591146&partnerID=8YFLogxK

U2 - 10.1109/ASAP.2015.7245709

DO - 10.1109/ASAP.2015.7245709

M3 - Conference contribution

AN - SCOPUS:84955591146

T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

SP - 68

EP - 69

BT - Proceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015

Y2 - 27 July 2015 through 29 July 2015

ER -

An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

Abstract

Publication series

Other

Access

OpenUrl availability

Other files and links

Fingerprint

Cite this