Abstract
Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs which are known to be more susceptible to short-term Vth degradation and recovery effects induced by Bias Temperature Instability (BTI). Experimental data shows that the proposed techniques can reduce the worst case DNL by 0.90 LSB and 0.77 LSB, respectively, compared to a typical SAR ADC.
Original language | English (US) |
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Title of host publication | 2015 IEEE Custom Integrated Circuits Conference, CICC 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781479986828 |
DOIs | |
State | Published - Nov 25 2015 |
Event | IEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States Duration: Sep 28 2015 → Sep 30 2015 |
Publication series
Name | Proceedings of the Custom Integrated Circuits Conference |
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Volume | 2015-November |
ISSN (Print) | 0886-5930 |
Other
Other | IEEE Custom Integrated Circuits Conference, CICC 2015 |
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Country/Territory | United States |
City | San Jose |
Period | 9/28/15 → 9/30/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- Short-term Vth instability
- aging
- analog circuit reliability
- bias temperature instability
- mitigation technique
- successive approximation register analog-to-digital converter