Abstract
Current trends in integrated circuit processing project gate insulators with oxide equivalent thicknesses of 1.5 to 1.0 nm. Gate oxides in this thickness range have oxide capacitances of 1 to 5 μF/cm2. When oxide capacitances are this large, traditional high-frequency capacitance-voltage techniques for measuring interface states can be inaccurate. We show that a combination of high and low frequency capacitance-voltage data, along with frequency dependent conductance methods, produce more accurate results.
| Original language | English (US) |
|---|---|
| Pages (from-to) | K491-K498 |
| Journal | Materials Research Society Symposium - Proceedings |
| Volume | 670 |
| DOIs | |
| State | Published - 2001 |
| Externally published | Yes |
| Event | Gate Stack and Silicide Issues in Silicon Processing II - San Francisco, CA, United States Duration: Apr 17 2001 → Apr 19 2001 |
Bibliographical note
Funding Information:This research was supported by Sematech and the Semiconductor Research Corporation under research ID number 616.018.