Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA

Sai Sanjeet; Bibhu Datta Sahoo; Keshab K. Parhi

doi:10.1109/MWSCAS47672.2021.9531878

Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA

Sai Sanjeet, Bibhu Datta Sahoo, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Scopus citations

Abstract

While many Fast Fourier Transform (FFT) architectures have been presented for computing real-valued FFT (RFFT), which of these architectures is best suited for low-throughput applications such as biomedical signals which are typically sampled between 256 Hz and 1 kHz remains unclear. This paper implements and compares throughput, resources, and energy consumption of three different hardware architectures for real-valued FFT algorithms using Xilinx Zynq-7000 FPGA. The RFFT architectures exploit the conjugate symmetry property of the real signals, thereby eliminating about half of the computations compared to a complex FFT. The three FFT architectures investigated in this paper include: single processing element (SPE), pipelined, and in-place. It is shown that, for a 256-point RFFT, using FPGA, the in-place architectures require the least device resources when compared to the pipelined architectures, while the throughput of the pipelined architectures is approximately 8 times that of the in-place architecture.

Original language	English (US)
Title of host publication	2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	112-115
Number of pages	4
ISBN (Electronic)	9781665424615
DOIs	https://doi.org/10.1109/MWSCAS47672.2021.9531878
State	Published - Aug 9 2021
Externally published	Yes
Event	2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Virtual, East Lansing, United States Duration: Aug 9 2021 → Aug 11 2021

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2021-August
ISSN (Print)	1548-3746

Conference

Conference	2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021
Country/Territory	United States
City	Virtual, East Lansing
Period	8/9/21 → 8/11/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

Fast Fourier Transform (FFT)
Real-Valued FFT
biomedical signals
in-place
pipelined
real-valued signals

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10.1109/MWSCAS47672.2021.9531878

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Sanjeet, S., Sahoo, B. D., & Parhi, K. K. (2021). Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA. In 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings (pp. 112-115). (Midwest Symposium on Circuits and Systems; Vol. 2021-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS47672.2021.9531878

Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA. / Sanjeet, Sai; Sahoo, Bibhu Datta; Parhi, Keshab K.
2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. p. 112-115 (Midwest Symposium on Circuits and Systems; Vol. 2021-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sanjeet, S, Sahoo, BD & Parhi, KK 2021, Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA. in 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings. Midwest Symposium on Circuits and Systems, vol. 2021-August, Institute of Electrical and Electronics Engineers Inc., pp. 112-115, 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021, Virtual, East Lansing, United States, 8/9/21. https://doi.org/10.1109/MWSCAS47672.2021.9531878

Sanjeet S, Sahoo BD, Parhi KK. Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA. In 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. p. 112-115. (Midwest Symposium on Circuits and Systems). doi: 10.1109/MWSCAS47672.2021.9531878

@inproceedings{9a4dc250805647f5929e0a57aaa19ee0,

title = "Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA",

abstract = "While many Fast Fourier Transform (FFT) architectures have been presented for computing real-valued FFT (RFFT), which of these architectures is best suited for low-throughput applications such as biomedical signals which are typically sampled between 256 Hz and 1 kHz remains unclear. This paper implements and compares throughput, resources, and energy consumption of three different hardware architectures for real-valued FFT algorithms using Xilinx Zynq-7000 FPGA. The RFFT architectures exploit the conjugate symmetry property of the real signals, thereby eliminating about half of the computations compared to a complex FFT. The three FFT architectures investigated in this paper include: single processing element (SPE), pipelined, and in-place. It is shown that, for a 256-point RFFT, using FPGA, the in-place architectures require the least device resources when compared to the pipelined architectures, while the throughput of the pipelined architectures is approximately 8 times that of the in-place architecture.",

keywords = "Fast Fourier Transform (FFT), Real-Valued FFT, biomedical signals, in-place, pipelined, real-valued signals",

author = "Sai Sanjeet and Sahoo, {Bibhu Datta} and Parhi, {Keshab K.}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 ; Conference date: 09-08-2021 Through 11-08-2021",

year = "2021",

month = aug,

day = "9",

doi = "10.1109/MWSCAS47672.2021.9531878",

language = "English (US)",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "112--115",

booktitle = "2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings",

}

TY - GEN

T1 - Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA

AU - Sanjeet, Sai

AU - Sahoo, Bibhu Datta

AU - Parhi, Keshab K.

PY - 2021/8/9

Y1 - 2021/8/9

N2 - While many Fast Fourier Transform (FFT) architectures have been presented for computing real-valued FFT (RFFT), which of these architectures is best suited for low-throughput applications such as biomedical signals which are typically sampled between 256 Hz and 1 kHz remains unclear. This paper implements and compares throughput, resources, and energy consumption of three different hardware architectures for real-valued FFT algorithms using Xilinx Zynq-7000 FPGA. The RFFT architectures exploit the conjugate symmetry property of the real signals, thereby eliminating about half of the computations compared to a complex FFT. The three FFT architectures investigated in this paper include: single processing element (SPE), pipelined, and in-place. It is shown that, for a 256-point RFFT, using FPGA, the in-place architectures require the least device resources when compared to the pipelined architectures, while the throughput of the pipelined architectures is approximately 8 times that of the in-place architecture.

AB - While many Fast Fourier Transform (FFT) architectures have been presented for computing real-valued FFT (RFFT), which of these architectures is best suited for low-throughput applications such as biomedical signals which are typically sampled between 256 Hz and 1 kHz remains unclear. This paper implements and compares throughput, resources, and energy consumption of three different hardware architectures for real-valued FFT algorithms using Xilinx Zynq-7000 FPGA. The RFFT architectures exploit the conjugate symmetry property of the real signals, thereby eliminating about half of the computations compared to a complex FFT. The three FFT architectures investigated in this paper include: single processing element (SPE), pipelined, and in-place. It is shown that, for a 256-point RFFT, using FPGA, the in-place architectures require the least device resources when compared to the pipelined architectures, while the throughput of the pipelined architectures is approximately 8 times that of the in-place architecture.

KW - Fast Fourier Transform (FFT)

KW - Real-Valued FFT

KW - biomedical signals

KW - in-place

KW - pipelined

KW - real-valued signals

UR - http://www.scopus.com/inward/record.url?scp=85115647920&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85115647920&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS47672.2021.9531878

DO - 10.1109/MWSCAS47672.2021.9531878

M3 - Conference contribution

AN - SCOPUS:85115647920

T3 - Midwest Symposium on Circuits and Systems

SP - 112

EP - 115

BT - 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021

Y2 - 9 August 2021 through 11 August 2021

ER -

Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA

Abstract

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Keywords

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