Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays

Nibedita Karmokar; Arvind K. Sharma; Jitesh Poojary; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar

doi:10.23919/DATE54114.2022.9774640

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays

Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

The accuracy and linearity of capacitive digital-to-analog converters (DACs) depend on precise capacitor ratios, but these ratios are perturbed by process variations and parasitics. This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted capacitors in charge-sharing DACs. Parasitics also degrade the switching speed of a capacitor array, particularly in FinFET nodes with severe wire/via resistances. To overcome this, the capacitor array is placed and routed to optimize switching speed, measured by the 3dB frequency. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

Original language	English (US)
Title of host publication	Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
Editors	Cristiana Bolchini, Ingrid Verbauwhede, Ioana Vatajelu
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	166-171
Number of pages	6
ISBN (Electronic)	9783981926361
DOIs	https://doi.org/10.23919/DATE54114.2022.9774640
State	Published - 2022
Event	2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 - Virtual, Online, Belgium Duration: Mar 14 2022 → Mar 23 2022

Publication series

Name	Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

Conference

Conference	2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
Country/Territory	Belgium
City	Virtual, Online
Period	3/14/22 → 3/23/22

Bibliographical note

Funding Information:
This work is supported in part by the DARPA IDEA program, as part of the ALIGN project, under SPAWAR Contract N660011824048.

Publisher Copyright:
© 2022 EDAA.

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10.23919/DATE54114.2022.9774640

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Karmokar, N., Sharma, A. K., Poojary, J., Madhusudan, M., Harjani, R., & Sapatnekar, S. S. (2022). Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. In C. Bolchini, I. Verbauwhede, & I. Vatajelu (Eds.), Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 (pp. 166-171). (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE54114.2022.9774640

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. / Karmokar, Nibedita; Sharma, Arvind K.; Poojary, Jitesh et al.
Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. ed. / Cristiana Bolchini; Ingrid Verbauwhede; Ioana Vatajelu. Institute of Electrical and Electronics Engineers Inc., 2022. p. 166-171 (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Karmokar, N, Sharma, AK, Poojary, J, Madhusudan, M, Harjani, R & Sapatnekar, SS 2022, Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. in C Bolchini, I Verbauwhede & I Vatajelu (eds), Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022, Institute of Electrical and Electronics Engineers Inc., pp. 166-171, 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022, Virtual, Online, Belgium, 3/14/22. https://doi.org/10.23919/DATE54114.2022.9774640

Karmokar N, Sharma AK, Poojary J, Madhusudan M, Harjani R , Sapatnekar SS. Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. In Bolchini C, Verbauwhede I, Vatajelu I, editors, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 166-171. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022). doi: 10.23919/DATE54114.2022.9774640

Karmokar, Nibedita ; Sharma, Arvind K. ; Poojary, Jitesh et al. / Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. editor / Cristiana Bolchini ; Ingrid Verbauwhede ; Ioana Vatajelu. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 166-171 (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).

@inproceedings{a141aeb4a1db45fabeec4cac9bef3502,

title = "Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays",

abstract = "The accuracy and linearity of capacitive digital-to-analog converters (DACs) depend on precise capacitor ratios, but these ratios are perturbed by process variations and parasitics. This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted capacitors in charge-sharing DACs. Parasitics also degrade the switching speed of a capacitor array, particularly in FinFET nodes with severe wire/via resistances. To overcome this, the capacitor array is placed and routed to optimize switching speed, measured by the 3dB frequency. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.",

author = "Nibedita Karmokar and Sharma, {Arvind K.} and Jitesh Poojary and Meghna Madhusudan and Ramesh Harjani and Sapatnekar, {Sachin S.}",

note = "Funding Information: This work is supported in part by the DARPA IDEA program, as part of the ALIGN project, under SPAWAR Contract N660011824048. Publisher Copyright: {\textcopyright} 2022 EDAA.; 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 ; Conference date: 14-03-2022 Through 23-03-2022",

year = "2022",

doi = "10.23919/DATE54114.2022.9774640",

language = "English (US)",

series = "Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "166--171",

editor = "Cristiana Bolchini and Ingrid Verbauwhede and Ioana Vatajelu",

booktitle = "Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022",

}

TY - GEN

T1 - Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays

AU - Karmokar, Nibedita

AU - Sharma, Arvind K.

AU - Poojary, Jitesh

AU - Madhusudan, Meghna

AU - Harjani, Ramesh

AU - Sapatnekar, Sachin S.

PY - 2022

Y1 - 2022

N2 - The accuracy and linearity of capacitive digital-to-analog converters (DACs) depend on precise capacitor ratios, but these ratios are perturbed by process variations and parasitics. This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted capacitors in charge-sharing DACs. Parasitics also degrade the switching speed of a capacitor array, particularly in FinFET nodes with severe wire/via resistances. To overcome this, the capacitor array is placed and routed to optimize switching speed, measured by the 3dB frequency. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

AB - The accuracy and linearity of capacitive digital-to-analog converters (DACs) depend on precise capacitor ratios, but these ratios are perturbed by process variations and parasitics. This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted capacitors in charge-sharing DACs. Parasitics also degrade the switching speed of a capacitor array, particularly in FinFET nodes with severe wire/via resistances. To overcome this, the capacitor array is placed and routed to optimize switching speed, measured by the 3dB frequency. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

UR - http://www.scopus.com/inward/record.url?scp=85126095826&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85126095826&partnerID=8YFLogxK

U2 - 10.23919/DATE54114.2022.9774640

DO - 10.23919/DATE54114.2022.9774640

M3 - Conference contribution

AN - SCOPUS:85126095826

T3 - Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

SP - 166

EP - 171

BT - Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

A2 - Bolchini, Cristiana

A2 - Verbauwhede, Ingrid

A2 - Vatajelu, Ioana

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

Y2 - 14 March 2022 through 23 March 2022

ER -

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays

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