Abstract
The issue of VLSI design of low latency/low power finite field multipliers is addressed and methods from logic structure, circuit design and physical mapping aspects are presented. With proposed architecture and physical mapping, an irregular balanced-tree parallel multiplier can be implemented as easy as a regular multiplier. The custom VLSI implementations of these multipliers over GF(28) show that the irregular multiplier has 53% smaller delay and 58% less power consumption than a regular multiplier.
Original language | English (US) |
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Pages (from-to) | IV574-IV577 |
Journal | Materials Research Society Symposium - Proceedings |
Volume | 626 |
State | Published - 2001 |
Event | Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: Apr 24 2000 → Apr 27 2000 |