Design Methodology of a 1.2-μm Double-Level-Metal CMOS Technology

Nancy E. Preckshot; Stephen A. Campbell; Walter W. Heikkila; Dimitri Dokos; Robin H. Passow; Wesley N. Grant; Dale Schultz; John P. Victorey

doi:10.1109/JSSC.1984.1052090

Design Methodology of a 1.2-μm Double-Level-Metal CMOS Technology

Nancy E. Preckshot, Stephen A. Campbell, Walter W. Heikkila, Dimitri Dokos, Robin H. Passow, Wesley N. Grant, Dale Schultz, John P. Victorey

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-μm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.

Original language	English (US)
Pages (from-to)	81-91
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	19
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.1984.1052090
State	Published - Feb 1984

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AU - Passow, Robin H.

AU - Grant, Wesley N.

AU - Schultz, Dale

AU - Victorey, John P.

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Design Methodology of a 1.2-μm Double-Level-Metal CMOS Technology

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