Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights

Yunzhi Duan; Shuai Li; Ruipeng Zhang; Qi Wang; Jienan Chen; Gerald E. Sobelman

doi:10.1109/ICDSP.2018.8631596

Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights

Yunzhi Duan, Shuai Li, Ruipeng Zhang, Qi Wang, Jienan Chen, Gerald E. Sobelman

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Scopus citations

Abstract

This paper presents an energy-efficient, deep parallel Convolutional Neural Network (CNN) accelerator. By adopting a recently proposed binary weight method, the CNN computations are converted into multiplication-free processing. To allow parallel accessing and storing of data, we use two RAM banks, where each bank is composed of NRAM blocks corresponding to N-parallel processing. We also design a reconfigurable CNN computing unit in a divide-and-reuse to support a variable-size convolutional filter. Compared with full-precision computing on the MNIST and CIFAR-10 classification tasks, the inference Top-1 accuracy of the binary weight CNN has dropped by 1.21% and 1.34%, respectively. The hardware implementation results show that the proposed design can achieve 2100 GOPs with a 4.6 millisecond processing latency. The deep parallel accelerator exhibits 3X energy efficiency compared to a GPU-based design.

Original language	English (US)
Title of host publication	2018 IEEE 23rd International Conference on Digital Signal Processing, DSP 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538668115
DOIs	https://doi.org/10.1109/ICDSP.2018.8631596
State	Published - Jul 2 2018
Event	23rd IEEE International Conference on Digital Signal Processing, DSP 2018 - Shanghai, China Duration: Nov 19 2018 → Nov 21 2018

Publication series

Name	International Conference on Digital Signal Processing, DSP
Volume	2018-November

Conference

Conference	23rd IEEE International Conference on Digital Signal Processing, DSP 2018
Country/Territory	China
City	Shanghai
Period	11/19/18 → 11/21/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

Convolutional Neural Network (CNN)
deep neural network
energy efficiency
parallel implementation

Access

10.1109/ICDSP.2018.8631596

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Full text

Cite this

Duan, Y., Li, S., Zhang, R., Wang, Q., Chen, J., & Sobelman, G. E. (2018). Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights. In 2018 IEEE 23rd International Conference on Digital Signal Processing, DSP 2018 Article 8631596 (International Conference on Digital Signal Processing, DSP; Vol. 2018-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICDSP.2018.8631596

Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights. / Duan, Yunzhi; Li, Shuai; Zhang, Ruipeng et al.
2018 IEEE 23rd International Conference on Digital Signal Processing, DSP 2018. Institute of Electrical and Electronics Engineers Inc., 2018. 8631596 (International Conference on Digital Signal Processing, DSP; Vol. 2018-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Duan, Y, Li, S, Zhang, R, Wang, Q, Chen, J & Sobelman, GE 2018, Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights. in 2018 IEEE 23rd International Conference on Digital Signal Processing, DSP 2018., 8631596, International Conference on Digital Signal Processing, DSP, vol. 2018-November, Institute of Electrical and Electronics Engineers Inc., 23rd IEEE International Conference on Digital Signal Processing, DSP 2018, Shanghai, China, 11/19/18. https://doi.org/10.1109/ICDSP.2018.8631596

Duan Y, Li S, Zhang R, Wang Q, Chen J, Sobelman GE. Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights. In 2018 IEEE 23rd International Conference on Digital Signal Processing, DSP 2018. Institute of Electrical and Electronics Engineers Inc. 2018. 8631596. (International Conference on Digital Signal Processing, DSP). doi: 10.1109/ICDSP.2018.8631596

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Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access

OpenUrl availability

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