TY - JOUR
T1 - Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions
AU - Lv, Yang
AU - Bloom, Robert P.
AU - Wang, Jian Ping
N1 - Publisher Copyright:
© 2010-2012 IEEE.
PY - 2019
Y1 - 2019
N2 - Recently proposed probabilistic spin logic (PSL) has offered promising solutions to novel computing applications, including some that have previously been covered by quantum computing. Several task implementations, including invertible logic gate, have been simulated numerically. Here, we report an experimental demonstration of a magnetic tunnel junction (MTJ) based hardware implementation of PSL. The probabilistic bit (p-bit) is the basic element of PSL. In our hardware implementation of a p-bit, two biasing methods, magnetic field and voltage, were used to better tune the characteristics of the MTJ random fluctuations. This addresses the potential system-wide speed limitations that result from the unavoidable device-to-device variation in MTJ fluctuation rates. With the p-bit hardware implementation demonstrated, we built three p-bits and connected them through a resistor network to implement an example PSL, an invertible and gate, which performs exactly as expected.
AB - Recently proposed probabilistic spin logic (PSL) has offered promising solutions to novel computing applications, including some that have previously been covered by quantum computing. Several task implementations, including invertible logic gate, have been simulated numerically. Here, we report an experimental demonstration of a magnetic tunnel junction (MTJ) based hardware implementation of PSL. The probabilistic bit (p-bit) is the basic element of PSL. In our hardware implementation of a p-bit, two biasing methods, magnetic field and voltage, were used to better tune the characteristics of the MTJ random fluctuations. This addresses the potential system-wide speed limitations that result from the unavoidable device-to-device variation in MTJ fluctuation rates. With the p-bit hardware implementation demonstrated, we built three p-bits and connected them through a resistor network to implement an example PSL, an invertible and gate, which performs exactly as expected.
KW - Spin electronics
KW - magnetic logic devices
KW - magnetic tunnel junctions
KW - magneto-electronics
KW - spin torque
KW - tunneling magnetoresistance
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U2 - 10.1109/LMAG.2019.2957258
DO - 10.1109/LMAG.2019.2957258
M3 - Article
AN - SCOPUS:85076264424
SN - 1949-307X
VL - 10
JO - IEEE Magnetics Letters
JF - IEEE Magnetics Letters
M1 - 8919996
ER -