FFT implementation with multi-operand floating point units

Zhang Zhang; Dongge Wang; Yuteng Pan; Dan Wang; Xiaofang Zhou; Gerald E Sobelman

doi:10.1109/ASICON.2011.6157160

FFT implementation with multi-operand floating point units

Zhang Zhang, Dongge Wang, Yuteng Pan, Dan Wang, Xiaofang Zhou, Gerald E Sobelman

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

In this paper we propose two new design techniques for floating point arithmetic units used in DSP applications, and apply them in the design of two multi-operand units for high-radix FFTs. These two multi-operand arithmetic units are a Modified two term Dot Product (MDP) unit and a Multi-operand Add-Sub unit (MAS). A radix-4 FFT butterfly computation block is implemented efficiently with these multi-operand units. Synthesis results show that the butterfly unit built with our design is about 43% faster and 9.5% smaller than a conventional implementation.

Original language	English (US)
Title of host publication	Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Pages	216-219
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2011.6157160
State	Published - Dec 1 2011
Event	2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China Duration: Oct 25 2011 → Oct 28 2011

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Other

Other	2011 IEEE 9th International Conference on ASIC, ASICON 2011
Country/Territory	China
City	Xiamen
Period	10/25/11 → 10/28/11

Keywords

Floating-point Arithmetic
Multi-operand Floating-point operations
Radix-4 FFT Butterfly

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Zhang, Z, Wang, D, Pan, Y, Wang, D, Zhou, X & Sobelman, GE 2011, FFT implementation with multi-operand floating point units. in Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011., 6157160, Proceedings of International Conference on ASIC, pp. 216-219, 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, 10/25/11. https://doi.org/10.1109/ASICON.2011.6157160

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title = "FFT implementation with multi-operand floating point units",

abstract = "In this paper we propose two new design techniques for floating point arithmetic units used in DSP applications, and apply them in the design of two multi-operand units for high-radix FFTs. These two multi-operand arithmetic units are a Modified two term Dot Product (MDP) unit and a Multi-operand Add-Sub unit (MAS). A radix-4 FFT butterfly computation block is implemented efficiently with these multi-operand units. Synthesis results show that the butterfly unit built with our design is about 43% faster and 9.5% smaller than a conventional implementation.",

keywords = "Floating-point Arithmetic, Multi-operand Floating-point operations, Radix-4 FFT Butterfly",

author = "Zhang Zhang and Dongge Wang and Yuteng Pan and Dan Wang and Xiaofang Zhou and Sobelman, {Gerald E}",

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AU - Zhang, Zhang

AU - Wang, Dongge

AU - Pan, Yuteng

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AU - Sobelman, Gerald E

PY - 2011/12/1

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N2 - In this paper we propose two new design techniques for floating point arithmetic units used in DSP applications, and apply them in the design of two multi-operand units for high-radix FFTs. These two multi-operand arithmetic units are a Modified two term Dot Product (MDP) unit and a Multi-operand Add-Sub unit (MAS). A radix-4 FFT butterfly computation block is implemented efficiently with these multi-operand units. Synthesis results show that the butterfly unit built with our design is about 43% faster and 9.5% smaller than a conventional implementation.

AB - In this paper we propose two new design techniques for floating point arithmetic units used in DSP applications, and apply them in the design of two multi-operand units for high-radix FFTs. These two multi-operand arithmetic units are a Modified two term Dot Product (MDP) unit and a Multi-operand Add-Sub unit (MAS). A radix-4 FFT butterfly computation block is implemented efficiently with these multi-operand units. Synthesis results show that the butterfly unit built with our design is about 43% faster and 9.5% smaller than a conventional implementation.

KW - Floating-point Arithmetic

KW - Multi-operand Floating-point operations

KW - Radix-4 FFT Butterfly

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FFT implementation with multi-operand floating point units

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