Abstract
The design of a hardware maze router with concurrent source/target wavefront propagation is described. The new design requires fewer clock cycles to find a shortest path than existing designs, and allows for a more efficient implementation of rip-up and reroute. Extensions to multipoint nets and multilayer carriers are included.
Original language | English (US) |
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Pages (from-to) | 373-374 |
Number of pages | 2 |
Journal | Electronics Letters |
Volume | 25 |
Issue number | 6 |
DOIs | |
State | Published - Sep 1 1989 |
Keywords
- Integrated circuits
- Printed circuits