Highly digital 1 GS/s 7-bit PWM ADC in 65 nm CMOS using time-domain quantisation

A 2 × time-interleaved 1 GS/s 7b ADC is presented, which uses pulse-width modulation and time domain quantisation for digitisation and is designed for wide channel bandwidths available at mm-wave frequencies. The area, resolution and power performance of the highly digital time-domain architecture is likely to scale with technology. The prototype ADC achieves 5.24 ENOB at a Nyquist rate while consuming 5.22 mW of power, resulting in a FOM_Walden,nyq = 138.13 fJ/ conversion step in TSMC’s 65 nm GP CMOS process.