Abstract
We studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified; (2) We presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed.
Original language | English (US) |
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Title of host publication | 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 |
Editors | R. Huang, M. Yu, J.J. Liou, T. Hiramito, C. Claeys |
Pages | 57-60 |
Number of pages | 4 |
Volume | 1 |
State | Published - Dec 1 2004 |
Event | 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China Duration: Oct 18 2004 → Oct 21 2004 |
Other
Other | 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 |
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Country/Territory | China |
City | Beijing |
Period | 10/18/04 → 10/21/04 |