Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography

Antian Wang; Weihang Tan; Keshab K. Parhi; Yingjie Lao

doi:10.1109/DFT56152.2022.9962361

Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography

Antian Wang, Weihang Tan, Keshab K. Parhi, Yingjie Lao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

With the surge of the powerful quantum computer, lattice-based cryptography proliferated the latest cryptography hardware implementation due to its resistance against quantum computers. Among the computational blocks of lattice-based cryptography, the random errors produced by the sampler play a key role in ensuring the security of these schemes. This paper proposes an integral architecture for the sampler, which can reduce the overall resource consumption by reusing the multipliers and adders within the modular polynomial computation. For instance, our experimental results show that the proposed design can effectively reduce the discrete Ziggurat sampling method in DSP usage.

Original language	English (US)
Title of host publication	Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
Editors	Luca Cassano, Sreejit Chakravarty, Alberto Bosio
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665459389
DOIs	https://doi.org/10.1109/DFT56152.2022.9962361
State	Published - 2022
Externally published	Yes
Event	35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 - Austin, United States Duration: Oct 19 2022 → Oct 21 2022

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume	2022-October
ISSN (Print)	2576-1501
ISSN (Electronic)	2765-933X

Conference

Conference	35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
Country/Territory	United States
City	Austin
Period	10/19/22 → 10/21/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

Discrete Gaussian Sampling
Lattice-Based Cryptography
Post-Quantum Cryptography

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10.1109/DFT56152.2022.9962361

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Wang, A., Tan, W., Parhi, K. K., & Lao, Y. (2022). Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography. In L. Cassano, S. Chakravarty, & A. Bosio (Eds.), Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT56152.2022.9962361

Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography. / Wang, Antian; Tan, Weihang; Parhi, Keshab K. et al.
Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022. ed. / Luca Cassano; Sreejit Chakravarty; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, A, Tan, W, Parhi, KK & Lao, Y 2022, Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography. in L Cassano, S Chakravarty & A Bosio (eds), Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, vol. 2022-October, Institute of Electrical and Electronics Engineers Inc., 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, United States, 10/19/22. https://doi.org/10.1109/DFT56152.2022.9962361

Wang A, Tan W, Parhi KK, Lao Y. Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography. In Cassano L, Chakravarty S, Bosio A, editors, Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022. Institute of Electrical and Electronics Engineers Inc. 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT56152.2022.9962361

Wang, Antian ; Tan, Weihang ; Parhi, Keshab K. et al. / Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography. Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022. editor / Luca Cassano ; Sreejit Chakravarty ; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

@inproceedings{b1e96b380bf2477685ad8f8095d1d774,

title = "Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography",

abstract = "With the surge of the powerful quantum computer, lattice-based cryptography proliferated the latest cryptography hardware implementation due to its resistance against quantum computers. Among the computational blocks of lattice-based cryptography, the random errors produced by the sampler play a key role in ensuring the security of these schemes. This paper proposes an integral architecture for the sampler, which can reduce the overall resource consumption by reusing the multipliers and adders within the modular polynomial computation. For instance, our experimental results show that the proposed design can effectively reduce the discrete Ziggurat sampling method in DSP usage.",

keywords = "Discrete Gaussian Sampling, Lattice-Based Cryptography, Post-Quantum Cryptography",

author = "Antian Wang and Weihang Tan and Parhi, {Keshab K.} and Yingjie Lao",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 ; Conference date: 19-10-2022 Through 21-10-2022",

year = "2022",

doi = "10.1109/DFT56152.2022.9962361",

language = "English (US)",

series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Luca Cassano and Sreejit Chakravarty and Alberto Bosio",

booktitle = "Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022",

}

TY - GEN

T1 - Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography

AU - Wang, Antian

AU - Tan, Weihang

AU - Parhi, Keshab K.

AU - Lao, Yingjie

PY - 2022

Y1 - 2022

N2 - With the surge of the powerful quantum computer, lattice-based cryptography proliferated the latest cryptography hardware implementation due to its resistance against quantum computers. Among the computational blocks of lattice-based cryptography, the random errors produced by the sampler play a key role in ensuring the security of these schemes. This paper proposes an integral architecture for the sampler, which can reduce the overall resource consumption by reusing the multipliers and adders within the modular polynomial computation. For instance, our experimental results show that the proposed design can effectively reduce the discrete Ziggurat sampling method in DSP usage.

AB - With the surge of the powerful quantum computer, lattice-based cryptography proliferated the latest cryptography hardware implementation due to its resistance against quantum computers. Among the computational blocks of lattice-based cryptography, the random errors produced by the sampler play a key role in ensuring the security of these schemes. This paper proposes an integral architecture for the sampler, which can reduce the overall resource consumption by reusing the multipliers and adders within the modular polynomial computation. For instance, our experimental results show that the proposed design can effectively reduce the discrete Ziggurat sampling method in DSP usage.

KW - Discrete Gaussian Sampling

KW - Lattice-Based Cryptography

KW - Post-Quantum Cryptography

UR - http://www.scopus.com/inward/record.url?scp=85143799859&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85143799859&partnerID=8YFLogxK

U2 - 10.1109/DFT56152.2022.9962361

DO - 10.1109/DFT56152.2022.9962361

M3 - Conference contribution

AN - SCOPUS:85143799859

T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT

BT - Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022

A2 - Cassano, Luca

A2 - Chakravarty, Sreejit

A2 - Bosio, Alberto

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022

Y2 - 19 October 2022 through 21 October 2022

ER -

Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography

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Keywords

Access

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