Interleaving of gate sizing and constructive placement for predictable performance

Sungjae Kim; Eugene Shragowitz; George Karypis; Rung Bin Lin

doi:10.1109/VDAT.2007.373225

Interleaving of gate sizing and constructive placement for predictable performance

Sungjae Kim, Eugene Shragowitz, George Karypis, Rung Bin Lin

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool.

Original language	English (US)
Title of host publication	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VDAT.2007.373225
State	Published - Sep 28 2007
Event	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan, Province of China Duration: Apr 25 2007 → Apr 27 2007

Publication series

Name	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Other

Other	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	4/25/07 → 4/27/07

Access

10.1109/VDAT.2007.373225

OpenUrl availability

Full text

Cite this

Kim, S., Shragowitz, E., Karypis, G., & Lin, R. B. (2007). Interleaving of gate sizing and constructive placement for predictable performance. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers Article 4239417 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373225

Interleaving of gate sizing and constructive placement for predictable performance. / Kim, Sungjae; Shragowitz, Eugene; Karypis, George et al.
2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239417 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, S, Shragowitz, E, Karypis, G & Lin, RB 2007, Interleaving of gate sizing and constructive placement for predictable performance. in 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers., 4239417, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007, Hsinchu, Taiwan, Province of China, 4/25/07. https://doi.org/10.1109/VDAT.2007.373225

Kim S, Shragowitz E, Karypis G, Lin RB. Interleaving of gate sizing and constructive placement for predictable performance. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239417. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). doi: 10.1109/VDAT.2007.373225

Kim, Sungjae ; Shragowitz, Eugene ; Karypis, George et al. / Interleaving of gate sizing and constructive placement for predictable performance. 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

@inproceedings{c1745356422f4d4e86c2a03e0c6d90e4,

title = "Interleaving of gate sizing and constructive placement for predictable performance",

abstract = "This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool.",

author = "Sungjae Kim and Eugene Shragowitz and George Karypis and Lin, {Rung Bin}",

year = "2007",

month = sep,

day = "28",

doi = "10.1109/VDAT.2007.373225",

language = "English (US)",

isbn = "1424405831",

series = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

booktitle = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

note = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 ; Conference date: 25-04-2007 Through 27-04-2007",

}

TY - GEN

T1 - Interleaving of gate sizing and constructive placement for predictable performance

AU - Kim, Sungjae

AU - Shragowitz, Eugene

AU - Karypis, George

AU - Lin, Rung Bin

PY - 2007/9/28

Y1 - 2007/9/28

N2 - This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool.

AB - This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool.

UR - http://www.scopus.com/inward/record.url?scp=34648824880&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34648824880&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2007.373225

DO - 10.1109/VDAT.2007.373225

M3 - Conference contribution

AN - SCOPUS:34648824880

SN - 1424405831

SN - 9781424405831

T3 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

BT - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

T2 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007

Y2 - 25 April 2007 through 27 April 2007

ER -

Interleaving of gate sizing and constructive placement for predictable performance

Abstract

Publication series

Other

Access

OpenUrl availability

Other files and links

Cite this