Learning from experience: Applying ML to analog circuit design

The problem of analog design automation has vexed several generations of researchers in electronic design automation. At its core, the dificulty of the problem is related to the fact that machine-generated designs have been unable to match the quality of the human designer. The human designer typically recognizes blocks from a netlist and draws upon her/his experience to translate these blocks into a circuit that is laid out in silicon. The ability to annotate blocks in a schematic or netlist-level description of a circuit is key to this entire process, but it is a process fraught with complexity due to the large number of variants of each circuit type. For example, the number of topologies of operational transconductance amplifiers (OTAs) easily numbers in the hundreds. A designer manages this complexity by dividing this large set of variants into classes (e.g., OTAs may be telescopic, folded cascode, etc.). Even so, the number of minor variations within each class is large. Early approaches to analog design automation attempted to use rule-based methods to capture these variations, but this database of rules required tender care: each new variant might require a new rule. As machine learning (ML) based alternatives have become more viable, alternative forms of solving this problem have begun to be explored. Our effort is part of the ALIGN (Analog Layout, Intelligently Generated from Netlists) project [2, 3], which is developing open-source software for analog/mixed-signal circuit layout [1]. Our specific goal is to translate a netlist into a physical layout, with 24-hour turnaround and no human in the loop. The ALIGN flow inputs a netlist whose topology and transistor sizes have already been chosen, a set of performance specifications, and a process design kit (PDK) that defines the process technology. The output of ALIGN is a layout in GDSII format. The philosophy of ALIGN is to use a mix of algorithmic techniques, template-driven design, and ML. ALIGN mimics the expert designer by identifying hierarchies within the netlist. These hierarchies correspond to building blocks of the design that can be assembled during layout, in the style of the human expert. At the lowest level of this hierarchy is an individual transistor; these transistors are then combined into larger fundamental primitives (e.g., differential pairs, current mirrors), then modules (e.g., OTAs), up through several levels of hierarchy to the system level. The ALIGN methodology is particularly useful in deeply scaled technologies, where the complexity of design rules implies a smaller design space for layout (e.g., due to unidirectional routing rules), combined with increased dificulty for the layout engineer in comprehending these rules, and has been applied to generate circuit layouts both in FinFET and in bulk technologies. This presentation overviews our experience in the use of machine learning based methods for analog design. Specifically, we touch upon (a) results from our efforts so far, (b) appropriate methods for mixing ML methods with traditional algorithmic techniques for solving the larger problem of analog layout, (c) limitations of ML methods, particularly in relation to the construction and availability of training sets, and (d) techniques for overcoming these limitations to deliver workable solutions for analog layout automation.