Memory size reduction for LDPC layered decoders

Shuang Zhao; Xiaofang Zhou; Fanglong Ying; Gerald E Sobelman

doi:10.1109/APCCAS.2010.5774863

Memory size reduction for LDPC layered decoders

Shuang Zhao, Xiaofang Zhou, Fanglong Ying, Gerald E Sobelman

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

LDPC coding has attracted much attention due to its high performance, and it has been widely used in telecommunication systems. This paper focuses on the decoder hardware architecture, especially on memory size reduction, which is an important part of the entire area cost. The design has been post-layout simulated using a UMC 0.18 micron technology at a clock speed of 74 MHz. Using the proposed 3-level memory structure together with the described control logic, the required number of bits of memory can be reduced by up to 34.9% compared to prior approaches.

Original language	English (US)
Title of host publication	Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages	426-429
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2010.5774863
State	Published - Dec 1 2010
Event	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia Duration: Dec 6 2010 → Dec 9 2010

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Country/Territory	Malaysia
City	Kuala Lumpur
Period	12/6/10 → 12/9/10

Keywords

LDPC
decoder
hierarchical memory organization
layered decoding
low density parity check code

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10.1109/APCCAS.2010.5774863

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Memory size reduction for LDPC layered decoders. / Zhao, Shuang; Zhou, Xiaofang; Ying, Fanglong et al.
Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. p. 426-429 5774863 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhao, S, Zhou, X, Ying, F & Sobelman, GE 2010, Memory size reduction for LDPC layered decoders. in Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010., 5774863, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 426-429, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, Malaysia, 12/6/10. https://doi.org/10.1109/APCCAS.2010.5774863

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Memory size reduction for LDPC layered decoders

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Keywords

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