Abstract
Computing the FFT of a single channel is well understood in the literature. However, computing the FFT of multiple channels in a systematic manner has not been fully addressed. This paper presents a framework to design a family of multi-channel FFT architectures using folding and interleaving. Three distinct multi-channel FFT architectures are presented in this paper. These architectures differ in the input and output preprocessing steps and are based on different folding sets, i.e., different orders of execution.
Original language | English (US) |
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Title of host publication | IEEE International Symposium on Circuits and Systems, ISCAS 2022 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 142-146 |
Number of pages | 5 |
ISBN (Electronic) | 9781665484855 |
DOIs | |
State | Published - 2022 |
Event | 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States Duration: May 27 2022 → Jun 1 2022 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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Volume | 2022-May |
ISSN (Print) | 0271-4310 |
Conference
Conference | 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 |
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Country/Territory | United States |
City | Austin |
Period | 5/27/22 → 6/1/22 |
Bibliographical note
Funding Information:This research was supported in part by the National Science Foundation under grant number CCF-1954749.
Publisher Copyright:
© 2022 IEEE.
Keywords
- FFT
- Folding
- Interleaving
- Multi-Channel FFT