Abstract
Power delivery network (PDN) design is a nontrivial, time-intensive, and iterative task. Correct PDN design must consider power bumps, currents, blockages, and signal congestion distribution patterns. This work proposes a machine learning-based methodology that employs a set of predefined PDN templates. At the floorplan stage, coarse estimates of current, congestion, macro/blockages, and C4 bump distributions are used to synthesize a grid for early design. At the placement stage, the grid is incrementally refined based on more accurate and fine-grained distributions of current and congestion. At each stage, a convolutional neural network (CNN) selects an appropriate PDN template for each region on the chip, building a safe-by-construction PDN that meets IR drop and electromigration (EM) specifications. The CNN is initially trained using a large synthetically created dataset, following which transfer learning is leveraged to bridge the gap between real-circuit data (with a limited dataset size) and synthetically generated data. On average, the optimization of the PDN frees thousands of routing tracks in congestion-critical regions, when compared to a globally uniform PDN, while staying within the IR drop and EM limits.
Original language | English (US) |
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Pages (from-to) | 3515-3528 |
Number of pages | 14 |
Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Volume | 41 |
Issue number | 10 |
DOIs | |
State | Published - Oct 1 2022 |
Bibliographical note
Publisher Copyright:© 1982-2012 IEEE.
Keywords
- Congestion
- deep neural network
- machine learning (ML)
- physical design
- power delivery network (PDN)
- transfer learning