Abstract
Editor's note:This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design.
Original language | English (US) |
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Pages (from-to) | 15-25 |
Number of pages | 11 |
Journal | IEEE Design and Test of Computers |
Volume | 26 |
Issue number | 5 |
DOIs | |
State | Published - 2009 |
Keywords
- 3D integration
- CMOS decap
- CMOS integrated circuits
- Capacitance
- Decoupling capacitors
- Design and test
- MIM decap
- Noise
- Optimization
- Power grid
- Power grids
- Three dimensional displays
- Tiles