Reduced complexity look-up table based π-rotation LDPC decoder

Hao Wang; Hongda Wang; Gerald E. Sobelman; Chiu Sing Choy

doi:10.1109/ICSICT.2016.7998936

Reduced complexity look-up table based π-rotation LDPC decoder

Hao Wang, Hongda Wang, Gerald E. Sobelman, Chiu Sing Choy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.

Original language	English (US)
Title of host publication	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings
Editors	Ru Huang, Ting-Ao Tang, Yu-Long Jiang
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	407-410
Number of pages	4
ISBN (Electronic)	9781467397179
DOIs	https://doi.org/10.1109/ICSICT.2016.7998936
State	Published - Jan 1 2016
Externally published	Yes
Event	13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Hangzhou, China Duration: Oct 25 2016 → Oct 28 2016

Publication series

Name	2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings

Other

Other	13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016
Country/Territory	China
City	Hangzhou
Period	10/25/16 → 10/28/16

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10.1109/ICSICT.2016.7998936

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Wang, H., Wang, H., Sobelman, G. E., & Choy, C. S. (2016). Reduced complexity look-up table based π-rotation LDPC decoder. In R. Huang, T.-A. Tang, & Y.-L. Jiang (Eds.), 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings (pp. 407-410). Article 7998936 (2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT.2016.7998936

Reduced complexity look-up table based π-rotation LDPC decoder. / Wang, Hao; Wang, Hongda; Sobelman, Gerald E. et al.
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings. ed. / Ru Huang; Ting-Ao Tang; Yu-Long Jiang. Institute of Electrical and Electronics Engineers Inc., 2016. p. 407-410 7998936 (2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, H, Wang, H, Sobelman, GE & Choy, CS 2016, Reduced complexity look-up table based π-rotation LDPC decoder. in R Huang, T-A Tang & Y-L Jiang (eds), 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings., 7998936, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 407-410, 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016, Hangzhou, China, 10/25/16. https://doi.org/10.1109/ICSICT.2016.7998936

Wang H, Wang H, Sobelman GE, Choy CS. Reduced complexity look-up table based π-rotation LDPC decoder. In Huang R, Tang TA, Jiang YL, editors, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. p. 407-410. 7998936. (2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings). doi: 10.1109/ICSICT.2016.7998936

Wang, Hao ; Wang, Hongda ; Sobelman, Gerald E. et al. / Reduced complexity look-up table based π-rotation LDPC decoder. 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings. editor / Ru Huang ; Ting-Ao Tang ; Yu-Long Jiang. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 407-410 (2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings).

@inproceedings{8817a4a631c245b289dfab617716ce14,

title = "Reduced complexity look-up table based π-rotation LDPC decoder",

abstract = "This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.",

author = "Hao Wang and Hongda Wang and Sobelman, {Gerald E.} and Choy, {Chiu Sing}",

year = "2016",

month = jan,

day = "1",

doi = "10.1109/ICSICT.2016.7998936",

language = "English (US)",

series = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "407--410",

editor = "Ru Huang and Ting-Ao Tang and Yu-Long Jiang",

booktitle = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings",

note = "13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 ; Conference date: 25-10-2016 Through 28-10-2016",

}

TY - GEN

T1 - Reduced complexity look-up table based π-rotation LDPC decoder

AU - Wang, Hao

AU - Wang, Hongda

AU - Sobelman, Gerald E.

AU - Choy, Chiu Sing

PY - 2016/1/1

Y1 - 2016/1/1

N2 - This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.

AB - This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.

UR - http://www.scopus.com/inward/record.url?scp=85028640697&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85028640697&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2016.7998936

DO - 10.1109/ICSICT.2016.7998936

M3 - Conference contribution

AN - SCOPUS:85028640697

T3 - 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings

SP - 407

EP - 410

BT - 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings

A2 - Huang, Ru

A2 - Tang, Ting-Ao

A2 - Jiang, Yu-Long

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016

Y2 - 25 October 2016 through 28 October 2016

ER -

Reduced complexity look-up table based π-rotation LDPC decoder

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