TY - JOUR
T1 - Robust gate sizing by geometric programming
AU - Singh, Jaskirat
AU - Nookala, Vidyasagar
AU - Luo, Zhi Quan
AU - Sapatnekar, Sachin
PY - 2005
Y1 - 2005
N2 - We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the process variations. An uncertainty ellipsoid method is used to model the random parameter variations. Spatial correlations of intra-die width and channel length variations are incorporated in the optimization procedure. The resulting optimization problem is relaxed to be a Geometric Program and is efficiently solved using convex optimization tools. The effectiveness of our robust gate sizing scheme is demonstrated by applying the optimization on the ISCAS '85 benchmark circuits and testing the optimized circuits by performing Monte Carlo simulations to model the process variations. By varying the size of the uncertainty ellipsoids, a trade-off between area and robustness is explored. Experimental results show that the timing yield of the robustly optimized circuits improves manifold over die traditional detcrministically sized circuits. As compared to the worst-case design, the robust gate sizing solution having the same area, has fewer timing violations.
AB - We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the process variations. An uncertainty ellipsoid method is used to model the random parameter variations. Spatial correlations of intra-die width and channel length variations are incorporated in the optimization procedure. The resulting optimization problem is relaxed to be a Geometric Program and is efficiently solved using convex optimization tools. The effectiveness of our robust gate sizing scheme is demonstrated by applying the optimization on the ISCAS '85 benchmark circuits and testing the optimized circuits by performing Monte Carlo simulations to model the process variations. By varying the size of the uncertainty ellipsoids, a trade-off between area and robustness is explored. Experimental results show that the timing yield of the robustly optimized circuits improves manifold over die traditional detcrministically sized circuits. As compared to the worst-case design, the robust gate sizing solution having the same area, has fewer timing violations.
KW - Geometric Program
KW - Posynomial
KW - Uncertainty ellipsoid
UR - http://www.scopus.com/inward/record.url?scp=27944492787&partnerID=8YFLogxK
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U2 - 10.1109/dac.2005.193824
DO - 10.1109/dac.2005.193824
M3 - Conference article
AN - SCOPUS:27944492787
SN - 0738-100X
SP - 315
EP - 320
JO - Proceedings - Design Automation Conference
JF - Proceedings - Design Automation Conference
M1 - 19.2
T2 - 42nd Design Automation Conference, DAC 2005
Y2 - 13 June 2005 through 17 June 2005
ER -