Status report on a MicroTCA card for HCAL Trigger and Readout at SLHC

We present recent measurements performed using a prototype MicroTCA card for CMS-HCAL Trigger and Readout at SLHC. Our second generation prototype uses a Xilinx XC5VFX70T FPGA to perform the high-speed communication and data processing for up to eight Readout Module fibers that are streaming data at 4.8 Gbps each. The FPGA also uses two SFP+ optical interfaces at 6.4 Gbps each for data transfer to the Trigger System. A local DAQ interface in the FPGA communicates via Gigabit Ethernet with the MicroTCA MCH. Bit Error Rate Test (BERT) results and data integrity analyses are presented in challenging clocking environments including a legacy TTC system. In addition, the status of the IPbus concept for control of deeply embedded devices is presented.