TY - JOUR
T1 - STEM
T2 - A scheme for two-phase evaluation of majority logic
AU - Mankalale, Meghna G.
AU - Liang, Zhaoxin
AU - Sapatnekar, Sachin S.
N1 - Publisher Copyright:
© 2002-2012 IEEE.
PY - 2017/7
Y1 - 2017/7
N2 - The switching time of a magnet in a spin-current-based majority gate depends on the input vector combination, and this often restricts the speed of majority-based circuits. To address this issue, this work proposes a novel two-phase scheme to implement majority logic and evaluates it on an all-spin logic (ASL) majority-based logic structures. In Phase 1, the output is initialized to a preset value. Next, in Phase 2, the inputs are evaluated to switch the output magnet to its correct value. The time window for the output to switch in Phase 2 is fixed. Using such a scheme, an $n$-input AND gate that requires a total of ( $2n-1$) inputs in the conventional implementation can now be implemented with only ($n+1$ ) inputs. When applied to standard logic functions, it is demonstrated that the proposed method of designing ASL gates is 1.6-3.4$\times$ faster and 1.9-6.9$\times$ more energy efficient than the conventional method, and for a five-magnet full adder, it is shown that the proposed ASL implementation is 1.5$\times$ faster, 2.2 $\times$ more energy efficient, and provides a 16% improvement in area.
AB - The switching time of a magnet in a spin-current-based majority gate depends on the input vector combination, and this often restricts the speed of majority-based circuits. To address this issue, this work proposes a novel two-phase scheme to implement majority logic and evaluates it on an all-spin logic (ASL) majority-based logic structures. In Phase 1, the output is initialized to a preset value. Next, in Phase 2, the inputs are evaluated to switch the output magnet to its correct value. The time window for the output to switch in Phase 2 is fixed. Using such a scheme, an $n$-input AND gate that requires a total of ( $2n-1$) inputs in the conventional implementation can now be implemented with only ($n+1$ ) inputs. When applied to standard logic functions, it is demonstrated that the proposed method of designing ASL gates is 1.6-3.4$\times$ faster and 1.9-6.9$\times$ more energy efficient than the conventional method, and for a five-magnet full adder, it is shown that the proposed ASL implementation is 1.5$\times$ faster, 2.2 $\times$ more energy efficient, and provides a 16% improvement in area.
KW - All-spin logic
KW - majority logic
KW - spintronics
KW - two-phase logic
UR - http://www.scopus.com/inward/record.url?scp=85029230081&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85029230081&partnerID=8YFLogxK
U2 - 10.1109/TNANO.2017.2695641
DO - 10.1109/TNANO.2017.2695641
M3 - Article
AN - SCOPUS:85029230081
SN - 1536-125X
VL - 16
SP - 606
EP - 615
JO - IEEE Transactions on Nanotechnology
JF - IEEE Transactions on Nanotechnology
IS - 4
M1 - 7904699
ER -