TY - JOUR
T1 - Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing
AU - Tang, Hua
AU - Zhang, Hui
AU - Doboli, Alex
PY - 2003
Y1 - 2003
N2 - This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.
AB - This paper describes a layout-aware analog synthesis methodology. The methodology includes parameter exploration and classification, parameter domain pruning and sampling, and identification of parameter dependencies. The optimization process executes a combined constraint transformation, floorplanning and global routing. The paper presents results for a high frequency continuous-time filter, and two ΣΔ ADCs. Compared to similar work, the methodology is more flexible in handling new designs, and more tolerant in accommodating layout parasitics.
KW - Continuous-time filter
KW - Synthesis
KW - ΣΔ modulator
UR - http://www.scopus.com/inward/record.url?scp=0038714051&partnerID=8YFLogxK
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U2 - 10.1145/764808.764861
DO - 10.1145/764808.764861
M3 - Conference article
AN - SCOPUS:0038714051
SN - 1066-1395
SP - 207
EP - 210
JO - Proceedings of the IEEE Great Lakes Symposium on VLSI
JF - Proceedings of the IEEE Great Lakes Symposium on VLSI
T2 - Proceedings of the 2003 ACM Great Lakes Symposium on VLSI
Y2 - 28 April 2003 through 29 April 2003
ER -