TY - JOUR
T1 - Synthesis of low power CMOS VLSI circuits using dual supply voltages
AU - Sundararajan, Vijay
AU - Parhi, Keshab K.
PY - 1999
Y1 - 1999
N2 - Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply voltage for gates off the critical path it is possible to dramatically reduce power consumption in CMOS VLSI circuits without performance degradation. Interfacing gates operating under multiple supply voltages, however, requires the use of level converters, which makes the problem modeling difficult. In this paper we develop a formal model and develop an efficient heuristic for addressing the use of two supply voltages for low power CMOS VLSI circuits without performance degradation. Power consumption savings up to 25% over and above the best known existing heuristics are demonstrated for combinational circuits in the ISCAS85 benchmark suite.
AB - Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply voltage for gates off the critical path it is possible to dramatically reduce power consumption in CMOS VLSI circuits without performance degradation. Interfacing gates operating under multiple supply voltages, however, requires the use of level converters, which makes the problem modeling difficult. In this paper we develop a formal model and develop an efficient heuristic for addressing the use of two supply voltages for low power CMOS VLSI circuits without performance degradation. Power consumption savings up to 25% over and above the best known existing heuristics are demonstrated for combinational circuits in the ISCAS85 benchmark suite.
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U2 - 10.1145/309847.309876
DO - 10.1145/309847.309876
M3 - Conference article
AN - SCOPUS:0032629489
SN - 0738-100X
SP - 72
EP - 75
JO - Proceedings - Design Automation Conference
JF - Proceedings - Design Automation Conference
T2 - 36th Annual Design Automation Conference, DAC 1999
Y2 - 21 June 1999 through 25 June 1999
ER -