TY - GEN
T1 - Triggered instructions
T2 - 40th Annual International Symposium on Computer Architecture, ISCA 2013
AU - Parashar, Angshuman
AU - Pellauer, Michael
AU - Adler, Michael
AU - Ahsan, Bushra
AU - Crago, Neal
AU - Lustig, Daniel
AU - Pavlov, Vladimir
AU - Zhai, Antonia
AU - Gambhir, Mohit
AU - Jaleel, Aamer
AU - Allmon, Randy
AU - Rayess, Rachid
AU - Maresh, Stephen
AU - Emer, Joel
PY - 2013
Y1 - 2013
N2 - In this paper, we present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid over-serialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture. Our analysis shows that a triggered-instruction based spatial accelerator can achieve 8× greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64% respectively over a program-counter style spatial baseline, resulting in a speedup of 2.0×.
AB - In this paper, we present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid over-serialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture. Our analysis shows that a triggered-instruction based spatial accelerator can achieve 8× greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64% respectively over a program-counter style spatial baseline, resulting in a speedup of 2.0×.
KW - Reconfigurable accelerators
KW - Spatial programming
UR - http://www.scopus.com/inward/record.url?scp=84881163269&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881163269&partnerID=8YFLogxK
U2 - 10.1145/2485922.2485935
DO - 10.1145/2485922.2485935
M3 - Conference contribution
AN - SCOPUS:84881163269
SN - 9781450320795
T3 - Proceedings - International Symposium on Computer Architecture
SP - 142
EP - 153
BT - ISCA 2013 - 40th Annual International Symposium on Computer Architecture, Conference Proceedings
Y2 - 23 June 2013 through 27 June 2013
ER -