Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond

Jin Cai; Amlan Majumdar; David Dobuzinsky; Tak H. Ning; Steven J. Koester; Wilfried E. Haensch

doi:10.1109/IEDM.2007.4419097

Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond

Jin Cai, Amlan Majumdar, David Dobuzinsky, Tak H. Ning, Steven J. Koester, Wilfried E. Haensch

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current I _OFF down to 10 pA/μm at supply voltage V_DD = 1.2 V. NFET/PFET drive current I_DSAT = 550/250 μA/tm at I_OFF = 100 pA/μm and gate length L_G ∼ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre-amorphization implants (PAI), source-side high-damage PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there is no fundamental limit for low leakage application of SOI.

Original language	English (US)
Article number	4419097
Pages (from-to)	907-910
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
DOIs	https://doi.org/10.1109/IEDM.2007.4419097
State	Published - Dec 1 2007
Event	2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States Duration: Dec 10 2007 → Dec 12 2007

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@article{8fcc65dc6d2342099a22a7af3f3a557c,

title = "Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond",

abstract = "We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current I OFF down to 10 pA/μm at supply voltage VDD = 1.2 V. NFET/PFET drive current IDSAT = 550/250 μA/tm at IOFF = 100 pA/μm and gate length LG ∼ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre-amorphization implants (PAI), source-side high-damage PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there is no fundamental limit for low leakage application of SOI.",

author = "Jin Cai and Amlan Majumdar and David Dobuzinsky and Ning, {Tak H.} and Koester, {Steven J.} and Haensch, {Wilfried E.}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/IEDM.2007.4419097",

language = "English (US)",

pages = "907--910",

journal = "Technical Digest - International Electron Devices Meeting, IEDM",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 IEEE International Electron Devices Meeting, IEDM ; Conference date: 10-12-2007 Through 12-12-2007",

}

TY - JOUR

T1 - Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond

AU - Cai, Jin

AU - Majumdar, Amlan

AU - Dobuzinsky, David

AU - Ning, Tak H.

AU - Koester, Steven J.

AU - Haensch, Wilfried E.

PY - 2007/12/1

Y1 - 2007/12/1

N2 - We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current I OFF down to 10 pA/μm at supply voltage VDD = 1.2 V. NFET/PFET drive current IDSAT = 550/250 μA/tm at IOFF = 100 pA/μm and gate length LG ∼ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre-amorphization implants (PAI), source-side high-damage PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there is no fundamental limit for low leakage application of SOI.

AB - We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current I OFF down to 10 pA/μm at supply voltage VDD = 1.2 V. NFET/PFET drive current IDSAT = 550/250 μA/tm at IOFF = 100 pA/μm and gate length LG ∼ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre-amorphization implants (PAI), source-side high-damage PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there is no fundamental limit for low leakage application of SOI.

UR - http://www.scopus.com/inward/record.url?scp=50349091701&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50349091701&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2007.4419097

DO - 10.1109/IEDM.2007.4419097

M3 - Conference article

AN - SCOPUS:50349091701

SN - 0163-1918

SP - 907

EP - 910

JO - Technical Digest - International Electron Devices Meeting, IEDM

JF - Technical Digest - International Electron Devices Meeting, IEDM

M1 - 4419097

T2 - 2007 IEEE International Electron Devices Meeting, IEDM

Y2 - 10 December 2007 through 12 December 2007

ER -

Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond

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