TY - GEN
T1 - Variation-aware speed binning of multi-core processors
AU - Sartori, John
AU - Pant, Aashish
AU - Kumar, Rakesh
AU - Gupta, Puneet
PY - 2010/5/28
Y1 - 2010/5/28
N2 - Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variation-aware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.
AB - Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variation-aware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.
KW - Binning
KW - Multi-core
KW - Performance
KW - Process variations
UR - http://www.scopus.com/inward/record.url?scp=77952656638&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77952656638&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2010.5450442
DO - 10.1109/ISQED.2010.5450442
M3 - Conference contribution
AN - SCOPUS:77952656638
SN - 9781424464555
T3 - Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010
SP - 307
EP - 314
BT - Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010
T2 - 11th International Symposium on Quality Electronic Design, ISQED 2010
Y2 - 22 March 2010 through 24 March 2010
ER -